Conventionally, an FPGA includes an array of configurable logic blocks (CLBs) and programmable input/output (I/O) blocks. The CLBs and I/O blocks are interconnected by a programmable interconnect structure that includes a large number of interconnect lines interconnected by programmable interconnect points (PIPs). PIPs are often coupled into groups that implement multiplexer circuits selecting one of several interconnect lines to provide a signal to a destination interconnect line or logic block. Some FPGAs also include additional logic blocks with special purposes, e.g., DLLs, RAM, and so forth.
One such FPGA, the Xilinx Virtex® FPGA, is described in detail in pages 3-75 through 3-96 of the Xilinx 2000 Data Book entitled “The Programmable Logic Data Book 2000” (hereinafter referred to as “the Xilinx Data Book”), published April, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. Young et al. further describe the interconnect structure of the Virtex FPGA in U.S. Pat. No. 5,914,616, issued Jun. 22, 1999 and entitled “FPGA Repeatable Interconnect Structure with Hierarchical Interconnect Lines”, which is incorporated herein by reference in its entirety.
One such FPGA, the Xilinx Virtex®-II FPGA, is described in detail in pages 33-75 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.
One such FPGA, the Xilinx Virtex®-II Pro™ FPGA, is described in detail in pages 19-71 of the “Virtex-II Pro Platform FPGA Handbook”, published October 14, 2002 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.
FPGAs may further include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.” Location of a processor block to embedded memory, such as block RAM (“BRAM”) for example, may negatively impact operation of an FPGA.
Accordingly, it would be desirable and useful to locate a processor block having one or more embedded processors relative to embedded memory to reduce the likelihood of such negative impact.